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Software-Controlled Instruction Prefetch Buffering for Low-End Processors

Qadri, MY and Qadri, NN and Fleury, M and McDonald-Maier, KD (2015) 'Software-Controlled Instruction Prefetch Buffering for Low-End Processors.' Journal of Circuits, Systems and Computers, 24 (10). ISSN 0218-1266

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Abstract

© 2015 World Scientific Publishing Company. This paper proposes a method of buffering instructions by software-based prefetching. The method allows low-end processors to improve their instruction throughput with a minimum of additional logic and power consumption. Low-end embedded processors do not employ caches for mainly two reasons. The first reason is that the overhead of cache implementation in terms of energy and area is considerable. The second reason is that, because a cache's performance primarily depends on the number of hits, an increasing number of misses could cause a processor to remain in stall mode for a longer duration. As a result, a cache may become more of a liability than an advantage. In contrast, the benchmarked results for the proposed software-based prefetch buffering without a cache show a 5-10% improvement in execution time. They also show a 4% or more reduction in the energy-delay-square-product (ED2P) with a maximum reduction of 40%. The results additionally demonstrate that the performance and efficiency of the proposed architecture scales with the number of multicycle instructions. The benchmarked routines tested to arrive at these results are widely deployed components of embedded applications.

Item Type: Article
Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Divisions: Faculty of Science and Health > Computer Science and Electronic Engineering, School of
Depositing User: Jim Jamieson
Date Deposited: 19 Nov 2015 12:25
Last Modified: 23 Jan 2019 02:15
URI: http://repository.essex.ac.uk/id/eprint/15495

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