Kanwal, N and McDonald-Maier, KD (2011) Memory-efficient design strategy for a parallel embedded integral image computation engine. In: UNSPECIFIED, ? - ?.

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Abstract

In embedded vision systems, parallel computation of the integral image presents several design challenges in terms of hardware resources, speed and power consumption. Although recursive equations significantly reduce the number of operations for computing the integral image, the required internal memory becomes prohibitively large for an embedded integral image computation engine for increasing image sizes. With the objective of achieving high-throughput with minimum hardware resources, this paper proposes a memory-efficient design strategy for a parallel embedded integral image computation engine. Results show that the design achieves nearly 35% reduction in memory for common HD video. © 2011 IEEE.

Item Type:	Conference or Workshop Item (Paper)
Additional Information:	Published proceedings: Proceedings - 2011 Irish Machine Vision and Image Processing Conference, IMVIP 2011
Subjects:	Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Divisions:	Faculty of Science and Health > Computer Science and Electronic Engineering, School of
Depositing User:	Clare Chatfield
Date Deposited:	29 May 2013 08:41
Last Modified:	08 Jan 2019 19:15
URI:	http://repository.essex.ac.uk/id/eprint/6196

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