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A fuzzy logic reconfiguration engine for symmetric chip multiprocessors

UNSPECIFIED (2010) A fuzzy logic reconfiguration engine for symmetric chip multiprocessors. In: UNSPECIFIED, ? - ?.

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Abstract

Recent developments in reconfigurable multiprocessor system on chip (MPSoC) have offered system designers a great amount of flexibility to exploit task concurrency with higher throughput and less energy consumption. This paper presents a novel fuzzy logic reconfiguration engine (FLRE) for coarse grain MPSoC reconfiguration that facilitates to identify an optimum balance between power and performance of the system. The FLRE is composed on two levels of abstraction layers. The system selects an optimal configuration of Level 1 / Level 2 cache size and Associativity, processor operating frequency and voltage, the number of cores based on miss rate, and energy and throughput information of the system both at core and SoC level. An 8-core symmetric chip multiprocessor has been used to evaluate the proposed scheme. The results show an overall decrease of energy consumption with not more than 30% decrease in the throughput. © 2010 IEEE.

Item Type: Conference or Workshop Item (Paper)
Additional Information: Published proceedings: CISIS 2010 - The 4th International Conference on Complex, Intelligent and Software Intensive Systems
Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Divisions: Faculty of Science and Health > Computer Science and Electronic Engineering, School of
Depositing User: Clare Chatfield
Date Deposited: 18 Sep 2013 11:37
Last Modified: 09 Jan 2019 02:15
URI: http://repository.essex.ac.uk/id/eprint/6852

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