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Low power processor architectures and contemporary techniques for power optimization - A review

Qadri, MY and Gujarathi, HS and McDonald-Maier, KD (2009) 'Low power processor architectures and contemporary techniques for power optimization - A review.' Journal of Computers, 4 (10). 927 - 942. ISSN 1796-203X

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Abstract

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER.

Item Type: Article
Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Divisions: Faculty of Science and Health > Computer Science and Electronic Engineering, School of
Depositing User: Clare Chatfield
Date Deposited: 18 Sep 2013 12:47
Last Modified: 23 Jan 2019 02:15
URI: http://repository.essex.ac.uk/id/eprint/6855

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