Deep Learning on FPGAs with Multiple Service Levels for Edge Computing

In the Internet of Things (IoT) era, deep learning is emerging as a promising approach for extracting information from IoT devices. Deep learning is also employed in the edge computing environment based on the demand for faster processing. In the edge server, various hardware accelerators have been proposed in recent studies to speed up the execution of such DNNs. One such accelerator is Xilinx’s Deep Learning Processor Unit (DPU), designed for FPGA-based systems. However, the limited resource capacity of FPGAs in these edge servers imposes an enormous challenge for such implementation. Recent research has shown a clear trade-off between the “resources consumed” vs. the “performance achieved Taking a cue from these findings, we address the problem of efficient implementation of deep learning into the edge computing environment in this paper. The edge server employs FPGAs for executing the deep learning model. Each deep learning network is equipped with multiple distinct implementations represented by different service levels based on resource usage (where a higher service level implies higher performance with high resource consumption). To this end, we propose an Integer Linear Programming based optimal solution strategy for selecting a service level to maximize the overall performance subject to a given resource bound. Proof-of-concept case study with a deep learning network of multiple service levels of DPUs on a physical FPGA has also been provided.