Chen, Chixiao and Yin, Jieming and Peng, Yarui and Palesi, Maurizio and Cao, Wenxu and Huang, Letian and Singh, Amit Kumar and Zhi, Haocong and Wang, Xiaohang (2022) Design Challenges of Intra- and Inter- Chiplet Interconnection. IEEE Design and Test, 39 (6). pp. 99-109. DOI https://doi.org/10.1109/mdat.2022.3203005
Chen, Chixiao and Yin, Jieming and Peng, Yarui and Palesi, Maurizio and Cao, Wenxu and Huang, Letian and Singh, Amit Kumar and Zhi, Haocong and Wang, Xiaohang (2022) Design Challenges of Intra- and Inter- Chiplet Interconnection. IEEE Design and Test, 39 (6). pp. 99-109. DOI https://doi.org/10.1109/mdat.2022.3203005
Chen, Chixiao and Yin, Jieming and Peng, Yarui and Palesi, Maurizio and Cao, Wenxu and Huang, Letian and Singh, Amit Kumar and Zhi, Haocong and Wang, Xiaohang (2022) Design Challenges of Intra- and Inter- Chiplet Interconnection. IEEE Design and Test, 39 (6). pp. 99-109. DOI https://doi.org/10.1109/mdat.2022.3203005
Abstract
This article discusses the challenges in intrachiplet and interchiplet networks, including the need for faster simulation, better architectures, and performance requirements determined by emerging applications.
| Item Type: | Article |
|---|---|
| Uncontrolled Keywords: | Chiplet; inter- and intra-chiplet interconnection |
| Divisions: | Faculty of Science and Health Faculty of Science and Health > Computer Science and Electronic Engineering, School of |
| SWORD Depositor: | Unnamed user with email elements@essex.ac.uk |
| Depositing User: | Unnamed user with email elements@essex.ac.uk |
| Date Deposited: | 18 Oct 2022 14:10 |
| Last Modified: | 18 Nov 2022 07:59 |
| URI: | http://repository.essex.ac.uk/id/eprint/33689 |
Available files
Filename: Design_Challenges_of_Intra-_and_Inter-_Chiplet_Interconnection.pdf