Lin, Tiantian and Qiu, Cheng and Wang, Xiaohang and Wang, Ling and Zheng, Zhulin and Jiang, Yingtao and Singh, Amit Kumar and Yin, Jieming and Qiu, Sihai and Li, Xiaodong and Tang, Xin and Song, Jie and Zhang, Mingzhe and Ren, Kui (2025) LEGOSim: A Unified Parallel Simulation Framework for Multi-chiplet Heterogeneous Integration. In: Micro 2025 IEEE/ACM International Symposium on Microarchitecture, 2025-10-18 - 2025-10-22, Seoul, Korea. (In Press)
Lin, Tiantian and Qiu, Cheng and Wang, Xiaohang and Wang, Ling and Zheng, Zhulin and Jiang, Yingtao and Singh, Amit Kumar and Yin, Jieming and Qiu, Sihai and Li, Xiaodong and Tang, Xin and Song, Jie and Zhang, Mingzhe and Ren, Kui (2025) LEGOSim: A Unified Parallel Simulation Framework for Multi-chiplet Heterogeneous Integration. In: Micro 2025 IEEE/ACM International Symposium on Microarchitecture, 2025-10-18 - 2025-10-22, Seoul, Korea. (In Press)
Lin, Tiantian and Qiu, Cheng and Wang, Xiaohang and Wang, Ling and Zheng, Zhulin and Jiang, Yingtao and Singh, Amit Kumar and Yin, Jieming and Qiu, Sihai and Li, Xiaodong and Tang, Xin and Song, Jie and Zhang, Mingzhe and Ren, Kui (2025) LEGOSim: A Unified Parallel Simulation Framework for Multi-chiplet Heterogeneous Integration. In: Micro 2025 IEEE/ACM International Symposium on Microarchitecture, 2025-10-18 - 2025-10-22, Seoul, Korea. (In Press)
Abstract
The rise of multi-chiplet integration challenges existing simulators like gem5 [ 45 ] and GPGPU-Sim [37 ] for efficiently simulating heterogeneous multiple-chiplet systems due to incapability to modularly integrate heterogenous chiplets, high synchronization overheads in parallel simulation, and high inter-chiplet communication modeling overhead. To address these limitations, this paper introduces LEGOSim, a unified parallel simulation framework capable of flexibly integrating various open-source and in-house designed chiplet simulators as processes in parallel simulation, referred to as "simlets" with minimal modifications needed. It introduces a three-stage simulation process that decouples chiplet simulation from inter-chiplet communication modeling to mitigate the communication modeling overhead. The framework also integrates Network-on-Interposer (NoI) simulator for modeling inter-chiplet communication, enabling accurate assessment of various interconnection architectures’ performance. Furthermore, it employs an on-demand synchronization protocol, ensuring synchronization only occurs when necessary, thus reducing overhead while maintaining correctness. Evaluated with diverse benchmarks, LEGOSim shows high accuracy in simulating multi-chiplet architectures like SIMBA [55 ] and a CiM-based accelerator [13 ], with average errors of 3.79% and 3.94%, respectively. It significantly reduces synchronization overhead by up to 99.9% compared to per-cycle synchronization and by 66.1% compared to time quantum synchronization, without synchronization errors. Five case studies show that LEGOSim also provides precise system performance metrics and stall cause reporting, simplifying tasks such as performance analysis and optimization, and can be used for design space exploration of various multi-chiplet systems.
Item Type: | Conference or Workshop Item (Paper) |
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Additional Information: | Published proceedings: _not provided_ |
Uncontrolled Keywords: | Simulator, architectural simulation, multi-chiplet system simulation |
Divisions: | Faculty of Science and Health > Computer Science and Electronic Engineering, School of |
SWORD Depositor: | Unnamed user with email elements@essex.ac.uk |
Depositing User: | Unnamed user with email elements@essex.ac.uk |
Date Deposited: | 15 Jul 2025 14:36 |
Last Modified: | 15 Jul 2025 14:37 |
URI: | http://repository.essex.ac.uk/id/eprint/41251 |