Determination of correct operation and behaviour of a structured amorphous surface

A recurring theme in intelligent environments is the intelligent surface composed of nanoscale processing units (smart dust). Such a surface (iSurface) can be considered an amorphous computer composed of a large array of identical processing units (iCells) each with its own sensor/effectors. An important requirement of such a surface is the need for a fast, reliable method to determine iCell operation, performance and code integrity. Any practical solution must fulfil certain criteria. First the impact on intercellular data communication bandwidth must be kept to a minimum, this is particularly important in high density, high speed iSurface applications such as high resolution video display. Previous work on processor profiling offered a possible solution in the form of metrics derived from profiling. This thesis describes a method developed to create long (>=32 bit) stable, robust metrics using a profiling technique that represents the current operational state of an iCell and thus enabling the quick exchange of diagnostics between iCells along with data traffic. Key requirements in the development of this system were fast acquisition of diagnostic variables, minimal affect on normal operation and the possibility of a hardware implementation which could be completely non intrusive in operation. The hardware developed fulfilled all these criteria in particular a novel method to create a stable metric that could determine compromised or incorrectly loaded code was developed. The metric of code integrity had both attributes of stability and responsiveness to change, something that has proven difficult to attain before. The uniqueness of the metrics produced by the hardware was also investigated and was determined to be very good and metric bit length was efficiently used. Impact on processor performance was also deemed acceptable at 2.31% and the developed architecture could theoretically be implemented in ‘system on chip’ (SOC) with zero processor overheads.