Gao, Cong and Zhu, xuqi and Saha, Sangeet and McDonald-Maier, Klaus and Zhai, Xiaojun (2023) Modelling and Analysis of FPGA-based MPSoC System with Multiple DNN Accelerators. In: 21st IEEE Interregional NEWCAS Conference - An IEEE CAS Society Interregional Flagship Conference, 2023-06-26 - 2023-06-28, Edinburgh.
Gao, Cong and Zhu, xuqi and Saha, Sangeet and McDonald-Maier, Klaus and Zhai, Xiaojun (2023) Modelling and Analysis of FPGA-based MPSoC System with Multiple DNN Accelerators. In: 21st IEEE Interregional NEWCAS Conference - An IEEE CAS Society Interregional Flagship Conference, 2023-06-26 - 2023-06-28, Edinburgh.
Gao, Cong and Zhu, xuqi and Saha, Sangeet and McDonald-Maier, Klaus and Zhai, Xiaojun (2023) Modelling and Analysis of FPGA-based MPSoC System with Multiple DNN Accelerators. In: 21st IEEE Interregional NEWCAS Conference - An IEEE CAS Society Interregional Flagship Conference, 2023-06-26 - 2023-06-28, Edinburgh.
Abstract
Deep Neural Networks (DNNs) have been widely applied in many fields for decades, and a standard method for deploying them on embedded systems involves using accelerators. However, due to the resource constraints of embedded systems, improving energy and computing efficiency becomes one of the research challenges in this domain. DNN model optimization and NAS (Neural Architecture Searching) are commonly used to strengthen the DNN model running efficiency on an embedded system. However, because the system’s runtime workloads are varied in practical situations, to further improve the computing efficiency of the system at runtime, real-time hardware and software design space exploration is required to ensure the system is running at the optimal time state at runtime. This paper presents a comprehensive modelling and analysis approach for the performance data (e.g., latency, energy consumption, accuracy, etc.) collected from an AMD-Xilinx heterogeneous MPSoC platform equipped with multiple DNN accelerators. The results demonstrate that the relationships between accuracy loss, hardware performance, and model size are significantly correlated. Furthermore, an appropriate hardware and software configuration could be obtained by giving constraints at runtime.
Item Type: | Conference or Workshop Item (Paper) |
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Additional Information: | Published proceedings: _not provided_ |
Uncontrolled Keywords: | FPGA; Heterogeneous embedded systems; MPSoC; Deep Neural networks; Edge computing; Energy efficiency |
Divisions: | Faculty of Science and Health Faculty of Science and Health > Computer Science and Electronic Engineering, School of |
SWORD Depositor: | Unnamed user with email elements@essex.ac.uk |
Depositing User: | Unnamed user with email elements@essex.ac.uk |
Date Deposited: | 12 Jan 2024 10:13 |
Last Modified: | 08 Nov 2024 02:28 |
URI: | http://repository.essex.ac.uk/id/eprint/35507 |
Available files
Filename: ieee_newcas (2).pdf
Licence: Creative Commons: Attribution 4.0