A new efficient multi‐task applications mapping for three‐dimensional Network‐on‐Chip based MPSoC

Three-dimensional Network-on-Chip (3D NoC) is a promising solution for solving 2D NoC problems while optimizing the system's performance. Mapping applications in 3D NoC is a crucial step as it has a significant impact on overall system performance. Moreover, multi-task supported processing elements (PEs) are needed to run multiple applications and provide more scalability. Most of the existing 3D mapping approaches consider only the single-task platform. In this paper, we propose an efficient multi-task mapping algorithm targeting regular 3D NoC that allows an incremental mapping and parallel execution of many applications onto different partitions on the 3D NoC. The proposed mapping algorithm is composed of three main steps aiming to reduce the communications overhead, exploiting the benefits of vertical links and improving the performances. The algorithm has been evaluated with various random and realistic benchmarks and compared with existing mapping algorithms for 3D NoC. The experimental results demonstrate that the proposed mapping strategy achieves significant performance in terms of communication cost, energy consumption and