Online detection of hardware Trojan enabled packet tampering attack on network-on-chip: A Bayesian approach

Hardware Trojans (HTs), proven difficult to be detected and removed at the offline post-silicon stage, can secretly launch dangerous packet tampering attacks on the network-on-chip (NoC) of a many-core chip. In this paper, we present an online HT detection scheme that is based on continuous, on-the-fly assessment of how likely any single node in the NoC includes an HT. In specific, the scheme first collects the routing path information of any data packet flowing through the NoC. The probability of a node being infected with HTs will next be determined based on each packet’s authentication result and this probability is iteratively updated through Bayesian analysis. A node shall be marked as a high-risk node, if its probability of infection exceeds a threshold, and all the high-risk nodes thus discovered will be bypassed by any future traffic. Since the proposed scheme only needs end-to-end authentication, as opposed to costly hop-to-hop authentication, the hardware overhead is kept low. To help further reduce the bandwidth and computation overheads, three approximate schemes are also proposed. Experiments have confirmed that the proposed HT detection methods can effectively locate the malicious nodes and thus reduce the infection rate to below 5%.