Gao, Cong and Saha, Sangeet and Zhu, Xuqi and Jing, Hongyuan and McDonald-Maier, Klaus D and Zhai, Xiaojun (2023) Application Level Resource Scheduling for Deep Learning Acceleration on MPSoC. Journal of Signal Processing Systems, 95 (10). pp. 1231-1243. DOI https://doi.org/10.1007/s11265-023-01881-9
Gao, Cong and Saha, Sangeet and Zhu, Xuqi and Jing, Hongyuan and McDonald-Maier, Klaus D and Zhai, Xiaojun (2023) Application Level Resource Scheduling for Deep Learning Acceleration on MPSoC. Journal of Signal Processing Systems, 95 (10). pp. 1231-1243. DOI https://doi.org/10.1007/s11265-023-01881-9
Gao, Cong and Saha, Sangeet and Zhu, Xuqi and Jing, Hongyuan and McDonald-Maier, Klaus D and Zhai, Xiaojun (2023) Application Level Resource Scheduling for Deep Learning Acceleration on MPSoC. Journal of Signal Processing Systems, 95 (10). pp. 1231-1243. DOI https://doi.org/10.1007/s11265-023-01881-9
Abstract
Deep Neutral Networks (DNNs) have been widely used in many applications, such as self-driving cars, natural language processing (NLP), image classification, visual object recognition, and so on. Field-programmable gate array (FPGA) based Multiprocessor System on a Chip (MPSoC) is recently considered one of the popular choices for deploying DNN models. However, the limited resource capacity of MPSoC imposes a challenge for such practical implementation. Recent studies revealed the trade-off between the “resources consumed" vs. the “performance achieved". Taking a cue from these findings, we address the problem of efficient implementation of deep learning into the resource-constrained MPSoC in this paper, where each deep learning network is run with different service levels based on resource usage (where a higher service level implies higher performance with increased resource consumption). To this end, we propose a heuristic-based strategy, Application Wise Level Selector (AWLS), for selecting service levels to maximize the overall performance subject to a given resource bound. AWLS can achieve higher performance within a constrained resource budget under various simulation scenarios. Further, we verify the proposed strategy using an AMD-Xilinx Zynq UltraScale+ XCZU9EG SoC. Using a framework designed to deploy multi-DNN on multi-DPUs (Deep Learning Units), it is proved that an optimal solution is achieved from the algorithm, which obtains the highest performance (Frames Per Second) using the same resource budget.
Item Type: | Article |
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Uncontrolled Keywords: | Deep Neutral networks; Embedded systems; FPGA; Hardware accelerator; MPSoC; Resource schedule strategy |
Divisions: | Faculty of Science and Health Faculty of Science and Health > Computer Science and Electronic Engineering, School of |
SWORD Depositor: | Unnamed user with email elements@essex.ac.uk |
Depositing User: | Unnamed user with email elements@essex.ac.uk |
Date Deposited: | 20 Jul 2023 19:53 |
Last Modified: | 30 Oct 2024 17:38 |
URI: | http://repository.essex.ac.uk/id/eprint/35952 |
Available files
Filename: s11265-023-01881-9.pdf
Licence: Creative Commons: Attribution 4.0