Acceleration of EEG signal processing on FPGA: A Step Towards Embedded BCI

This paper presents a research project focused on leveraging Field-Programmable Gate Arrays (FPGAs) to enhance the performance and efficiency of Finite Impulse Response (FIR) filters in EEG signal processing, specifically targeting motor imagery detection. By harnessing the parallelism and customization capabilities of FPGAs, we aim to achieve significant improvements in execution time and throughput. The proposed methodology involves customizing and integrating the FIR filter IP core from the Xilinx IP catalog using Xilinx Vivado, alongside MATLAB's Frequency Domain Analysis (FDA) tool for designing optimized filter coefficients tailored to EEG signal processing requirements. The research project encompasses key steps, including the customization of the FIR filter IP core, the creation of a design overlay incorporating the accelerator IP and configuration components, the generation of a bitstream for the ZYNQ board, and the evaluation of the hardware implementation's performance against software-based FIR filters. Performance metrics such as execution time, throughput, and energy efficiency are assessed to validate the superiority of the developed hardware accelerator. Our results demonstrate the significant advantages of hardware-accelerated FIR filters over software-based implementations. The hardware execution time is approximately 12.61 times faster than the software execution time, enabling faster real-time processing of EEG signals. Additionally, the hardware implementation exhibits improved throughput and energy efficiency, making it well-suited for resource-constrained environments. These findings pave the way for the implementation of brain-computer interfaces (BCI) on edge devices for more portable and deployable solutions.