Wang, Xiaohang and Wang, Yifan and Jiang, Yingtao and Singh, Amit Kumar and Yang, Mei (2024) On Task Mapping in Multi-chiplet Based Many-core Systems to Optimize Inter- and Intra-chiplet Communications. IEEE Transactions on Computers. pp. 1-14. DOI https://doi.org/10.1109/tc.2024.3500354 (In Press)
Wang, Xiaohang and Wang, Yifan and Jiang, Yingtao and Singh, Amit Kumar and Yang, Mei (2024) On Task Mapping in Multi-chiplet Based Many-core Systems to Optimize Inter- and Intra-chiplet Communications. IEEE Transactions on Computers. pp. 1-14. DOI https://doi.org/10.1109/tc.2024.3500354 (In Press)
Wang, Xiaohang and Wang, Yifan and Jiang, Yingtao and Singh, Amit Kumar and Yang, Mei (2024) On Task Mapping in Multi-chiplet Based Many-core Systems to Optimize Inter- and Intra-chiplet Communications. IEEE Transactions on Computers. pp. 1-14. DOI https://doi.org/10.1109/tc.2024.3500354 (In Press)
Abstract
Multi-chiplet system design, by integrating multiple chiplets/dielets within a single package, has emerged as a promising paradigm in the post-Moore era. This paper introduces a novel task mapping algorithm for multi-chiplet many-core systems, addressing the unique challenges posed by intra- and inter-chiplet communications under power and thermal constraints. Traditional task mapping algorithms fail to account for the latency and bandwidth differences between these communications, leading to sub-optimal performance in multi-chiplet systems. Our proposed algorithm employs a two-step process: (1) task assignment to chiplets using binary linear programming, leveraging a totally unimodular constraint matrix, and (2) intra-chiplet mapping that minimizes communication latency while considering both thermal and power constraints. This method strategically positions tasks with extensive inter-chiplet communication near interface nodes and centralizes those with predominant intra-chiplet communication. Experimental results demonstrate that the proposed algorithm outperforms existing methods (DAR and IOA) with a 37.5% and 24.7% reduction in execution time, respectively. Communication latency is also reduced by up to 43.2% and 32.9%, compared to DAR and IOA. These findings affirm that the proposed task mapping algorithm aligns well with the characteristics of multi-chiplet based many-core systems, and thus improves optimal performance.
Item Type: | Article |
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Uncontrolled Keywords: | Many-core systems; Chiplet; Task mapping; Performance optimization |
Divisions: | Faculty of Science and Health Faculty of Science and Health > Computer Science and Electronic Engineering, School of |
SWORD Depositor: | Unnamed user with email elements@essex.ac.uk |
Depositing User: | Unnamed user with email elements@essex.ac.uk |
Date Deposited: | 29 Oct 2024 13:54 |
Last Modified: | 30 Nov 2024 22:59 |
URI: | http://repository.essex.ac.uk/id/eprint/39509 |
Available files
Filename: TC-2023-10-0563.R1-main..pdf