Molahosseini, Amir Sabbagh and Lee, JunKyu and Vandierendonck, Hans (2025) Software-Defined Number Formats for High-Speed Belief Propagation. IEEE Transactions on Emerging Topics in Computing. pp. 1-14. DOI https://doi.org/10.1109/tetc.2025.3528972
Molahosseini, Amir Sabbagh and Lee, JunKyu and Vandierendonck, Hans (2025) Software-Defined Number Formats for High-Speed Belief Propagation. IEEE Transactions on Emerging Topics in Computing. pp. 1-14. DOI https://doi.org/10.1109/tetc.2025.3528972
Molahosseini, Amir Sabbagh and Lee, JunKyu and Vandierendonck, Hans (2025) Software-Defined Number Formats for High-Speed Belief Propagation. IEEE Transactions on Emerging Topics in Computing. pp. 1-14. DOI https://doi.org/10.1109/tetc.2025.3528972
Abstract
This paper presents the design and implementation of Software-Defined Floating-Point (SDF) number formats for high-speed implementation of the Belief Propagation (BP) algorithm. SDF formats are designed specifically to meet the numeric needs of the computation and are more compact representations of the data. They reduce memory footprint and memory bandwidth requirements without sacrificing accuracy, given that BP for loopy graphs inherently involves algorithmic errors. This paper designs several SDF formats for sum-product BP applications by careful analysis of the computation. Our theoretical analysis leads to the design of 16-bit (half-precision) and 8-bit (mini-precision) widths. We moreover present highly efficient software implementation of the proposed SDF formats which is centered around conversion to hardware-supported single-precision arithmetic hardware. Our solution demonstrates negligible conversion overhead on commercially available CPUs. For Ising grids with sizes from 100×100 to 500×500, the 16- and 8-bit SDF formats along with our conversion module produce equivalent accuracy to double-precision floating-point format but with 2.86× speedups on average on an Intel Xeon processor. Particularly, increasing the grid size results in higher speed-up. For example, the proposed half-precision format with 3-bit exponent and 13-bit mantissa achieved the minimum and maximum speedups of 1.30× and 1.39× over single-precision, and 2.55× and 3.40× over double-precision, by increasing grid size from 100×100 to 500×500.
Item Type: | Article |
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Uncontrolled Keywords: | Reduced-Precision Floating-Point Number Format; Belief Propagation; Transprecise Computing; Software-Defined Number Format |
Divisions: | Faculty of Science and Health Faculty of Science and Health > Computer Science and Electronic Engineering, School of |
SWORD Depositor: | Unnamed user with email elements@essex.ac.uk |
Depositing User: | Unnamed user with email elements@essex.ac.uk |
Date Deposited: | 24 Jan 2025 17:53 |
Last Modified: | 24 Jan 2025 17:53 |
URI: | http://repository.essex.ac.uk/id/eprint/40105 |
Available files
Filename: accepted_version_BP_Float.pdf